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HFA3766
PRELIMINARY
January 1999
File Number 4328.1
400MHz AGC Quadrature IF Modulator/Demodulator
The HFA3766 is a highly integrated baseband converter for quadrature modulation applications. It features all the necessary blocks for baseband modulation and demodulation of I and Q signals. It has a two stage integrated AGC IF amplifier with 82dB of voltage gain and 76dB of gain control range. Baseband antialiasing is integrated into the design. Four filter bandwidths are programmable via a two bit digital control interface. In addition, these filters are continuously tunable over a 20% frequency range via one external resistor. For baseband modulation digital I and Q data are delivered to the transmit section. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of modulation and demodulation. A selectable buffered divide by 2 LO output and a stable reference voltage are provided for convenience of the user. The device is housed in a thin 80 lead TQFP package well suited for PCMCIA board applications.
TM
Features
* * * * * * * * * * * * * * * * * Integrates all IF Transmit and AGC Receive Functions Broad Frequency Range . . . . . . . . . . 10MHz to 400MHz I/Q Amplitude and Phase Balance . . . . 0.2dB, 2 Degrees 5th Order Programmable Low Pass Filter . . . . . . . . . . . . . . . . . . 2.2MHz to 17.6MHz 400MHz AGC Gain Strip . . . . . . . . . . . . . . . . . . . . . 82dB AGC Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75dB Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm Fast AGC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 1s Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . . . . 1s Power Management/Standby Mode Single Supply 3.0V Operation Wireless Local Loop Wireless Local Area Networks PCMCIA Wireless Transceivers ISM Systems CDMA Radios PCS/Wireless PBX
Ordering Information
PART NUMBER HFA3766IN HFA3766IN96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 80 Ld TQFP Tape and Reel PKG. NO. Q80.14x14
Simplified
DEMOD_RXI DEMOD_RXQ LPF_TUNE_1 LPF_TUNE_0 DEMOD_IFIN AGC1_OUT AGC2_OUT LPF_SEL0 LPF_SEL1 LPF_RXQ LPF_RXI AGC2_IN
AGC_SEl AGC1_IN AGC1_VAGC AGC2_VAGC LO_IN /2 0o/90o LO_OUT LO_GND MOD_TX_IF_OUT 2V REF TX D OR A MOD_TXQ MOD_TXI LPF_TXI LPF_TXQ
LPF_RXI_OUT LPF_RXQ _OUT M U X LPF_TXI_IN Q LPF_TXQ_IN
I M U X
1
2V REF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. PRISM and PRISM logo are trademarks of Intersil Corporation. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HFA3766 Pinout
80 LEAD TQFP TOP VIEW
AGC1_VAGC GND AGC1_VCC AGC1_PE AGC1_OUT+ AGC1_OUTAGC1_VCC GND GND GND GND GND GND GND GND AGC2_BYPAGC2_INGND AGC2_IN+ AGC2_BYP+ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AGC1_BYP+ AGC1_IN+ GND AGC1_SEL AGC1_INAGC1_BYPGND GND LPF_VCC 2V REF LPF_BYP LPF_TXI_IN LPF_TXQ_IN LPF_RXI_OUT LPF_RXQ_OUT LPF_SEL1 LPF_SEL0 LPF_TUNE1 LPF_TUNE0 TX D OR A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LPF_RX_PE LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND GND DEMOD_RXI+ DEMOD_RXIDEMOD_RXQ+ DEMOD_RXQMOD_TXI+ MOD_TXIMOD_TXQ+ MOD_TXQ60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGC2_VAGC GND AGC2_VCC AGC2_PE AGC2_OUT+ AGC2_OUTAGC2_VCC GND GND GND LO_GND DEMOD_IFINDEMOD_IFIN+ MOD_VCC LO_OUT MOD_VCC LO_IN DEMOD_RX_PE MOD_TX_IF_OUT MOD_TX_PE
Typical Application Diagram
HFA3766 (FILE# 4328) HFA3424 (NOTE) (FILE# 4131) I HFA3624 RF/IF CONVERTER (FILE# 4066) M U X M U X RXQ VAGC TUNE/SELECT RXI
/2
0o/90o
M U X
RFPA HFA3925 (FILE# 4132)
VCO VCO
Q
QUAD IF MODEM DUAL SYNTHESIZER HFA3524 (FILE# 4062)
TX D OR A
PRISMTM CHIP SET FILE #4063
For additional information on the PRISMTM Full Duplex Radio Chip Set, call (407) 724-7800 to access Intersil's AnswerFAX system. When prompted, key in the four-digit document number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in Typical Application Diagram, and correspond to the appropriate circuit.
2
HFA3766 Block Diagram
LPF_RXQ_OUT
LPF_RXI_OUT
MUX_LPF
LPF_SEL1 LPF_SEL0 LPF_TUNE0 LPF_TUNE1 LPF_RX_PE LPF_RXI LPF_RXI + LPF_RXQ + LPF_RXQ DEMOD_RXQ DEMOD_RXQ + DEMOD_RXI DEMOD_RXI + DEMOD_RX_PE Q MUX I MUX
LPF_TXQ_IN
LPF_TXI_IN
TX D OR A
LPF_TX_PE
LPF_TXQ LPF_TXQ + LPF_TXI LPF_TXI +
DOWN CONV
90o
MOD _TXI + MOD _TXI MOD _TXQ + MOD _TXQ MOD_TX_PE
DEDEMOD_IFIN+ DEMOD_IFIN AGC2_OUT AGC2_OUT + AGC2_PE 1000p AGC2_IN+ AGC2_INAGC1_OUT AGC1_OUT + 33p 10nH NO FIT AGC 56 56 AGC1_PE SAW AGC1_IN+ IF
/2
0o
/
UP CONVERTER
1000p
IF
2V REF
2V REF
AGC1_INAGC1_VAGC
AGC2_VAGC
(2XLO)
LO_GND
LO_IN
IF IN
50
NOTE: VCC , GND and Bypass capacitors not shown.
3
MOD_TX IF_OUT
LO_OUT
VAGC
LPF_BYP 1.25V
VCC
HFA3766 Pin Descriptions
PIN 1 SYMBOL AGC1_BYP+ DESCRIPTION DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Non-inverting analog input of AGC amplifier 1. Ground. Connect to a solid ground plane. This pin selects either differential or single ended input configuration for the first stage AGC. Ground this pin for differential input configuration. Leave it floating for single ended input configuration. Inverting analog input of AGC amplifier 1. DC feedback pin for AGC amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. Stable 2V reference voltage output for external applications. Loading must be higher than 10k. A bypass capacitor of at least 0.1F is required. Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1F decoupling capacitor. Low pass filter in phase (I) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs Low pass filter in phase (I) channel receive output. Requires AC coupling. Low pass filter quadrature (Q) channel receive output. Requires AC coupling. Digital control input pins. Selects four programmed cut off frequencies for the receive channel. Tuning speed from one cutoff to another is less than 1s. SEL1 LO LO SEL0 LO HI CUTOFF FREQUENCY 2.2MHz 4.4MHz SEl1 HI HI SEl0 LO HI CUTOFF FREQUENCY 8.8MHz 17.6MHz
2 3 4
AGC1_IN+ GND AGC_SEL
5 6
AGC1_INAGC1_BYP-
7, 8 9 10
GND LPF_VCC 2V REF
11
LPF_BYP
12
LPF_TXI_IN
13
LPF_TXQ_IN
14 15 16 17
LPF_RX_I LPF_RX_Q LPF_SEL1 LPF_SEL0
18 19 20 21 22 23
LPF_TUNE1 LPF_TUNE0 TXD or TXA LPF_RX_PE LPF_TX_PE LPF_TXQ-
These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC specifications. Selects between digital or analog signals. Tie to GND for digital. Tie to VCC for analog. Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High. Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High. Negative output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40. Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39. Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the inverting input of the in phase Modulator (Mod_TXI-), pin 38. Positive output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the non inverting input of the in phase Modulator (Mod_TXI+), pin 37. Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36.
24
LPF_TXQ+
25
LPF_TXI-
26
LPF_TXI+
27
LPF_RXQ-
4
HFA3766 Pin Descriptions
PIN 28 (Continued) DESCRIPTION Low pass filter non inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35. Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34. Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the positive output of the in phase demodulator (DEMOD_RXI-), pin 33. Ground. Connect to a solid ground plane. In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXI+), pin 30. In phase demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXI-), pin 29. Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXQ+), pin 28. Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXQ+), pin 27. In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXI+), pin 26. In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXI-), pin 25. Quadrature modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXQ+), pin 24. Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXQ-), pin 23. Digital input control to enable the Modulator section. Enable logic level is High for transmit. Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 316. Digital input control to enable the demodulator section. Enable logic level is High.
SYMBOL LPF_RXQ+
29
LPF_RXI-
30
LPF_RXI+
31, 32 33
GND DEMOD_RXI+
34
DEMOD_RXI-
35
DEMOD_RXQ+
36
DEMOD_RXQ-
37
MOD_TXI+
38
MOD_TXI-
39
MOD_TXQ+
40
MOD_TXQ-
41 42
MOD_TX_PE MOD_TX_IF _OUT DEMOD_RX _PE LO_In (2XLO)
43
44
Single ended local oscillator current input. Frequency of input signal must be twice the required demodulator LO frequency. Input current is optimum at 200ARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130. This pin requires AC coupling. NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin. Divide by 2 buffered output reference from "DEMOD_LO_in" input. Used for external applications where the demodulating carrier reference frequency is required. 50 single end driving capability. This output can be disabled by use of pin 50. AC coupling is required. Supply pin for the Demodulator. Use high quality decoupling capacitors right at the pin. Demodulator, non-inverting input. Requires AC coupling. Demodulator, inverting input. Requires AC coupling. When grounded, this pin enables the LO buffer (DEMOD_LO_Out). When open (NC) it disables the LO buffer. Ground. Connect to a solid ground plane. Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin.
45 46
MOD_VCC LO_Out
47 48 49 50 51, 52, 53 54
MOD_VCC DEMOD_IFIN+ DEMOD_IFINLO_GND GND AGC2_VCC
5
HFA3766 Pin Descriptions
PIN 55 56 57 58 59 60 61 (Continued) DESCRIPTION Positive output of AGC amplifier 2. Requires AC coupling. Negative output of AGC amplifier 2. Requires AC coupling. Digital input control to enable the AGC amplifier 2. Enable logic level is High. Supply pin for the AGC amplifier 2. Use high quality decoupling capacitors right at the pin. Ground. Connect to a solid ground plane. AGC amplifier 2, AGC control input. DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Non-inverting analog input of AGC amplifier 2. Ground. Connect to a solid ground plane. Inverting input of AGC amplifier 2. DC feedback pin for AGC amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. Negative output of AGC amplifier 1. Requires AC coupling. Positive output of AGC amplifier 1. Requires AC coupling. Digital input control to enable the AGC amplifier 1. Enable logic level is High. AGC amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. Ground. Connect to a solid ground plane. AGC amplifier 1, AGC control input.
SYMBOL AGC2_OUTAGC2_OUT+ AGC2_PE AGC2_VCC GND AGC2_VAGC AGC2_BYP+
62 63 64 65
AGC2_IN+ GND AGC2_INAGC2_BYP-
66 - 73 74 75 76 77 78 79 80
GND AGC1_VCC AGC1_OUTAGC1_OUT+ AGC1_PE AGC1_VCC GND AGC1_VAGC
6
HFA3766
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Package Power Dissipation at 70oC TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1W Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . -65oC TA 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (TQFP - Lead Tips Only)
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40oC TA 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Cascaded DC Electrical Specifications
PARAMETER Total Supply Current, at 5.5V Shutdown (Standby) Current at 5.5V All Digital Inputs VIH (TTL Threshold for All VCC) All Digital Inputs VIL (TTL Threshold for All VCC)
VCC = 4.5V to 5.5V, Unless Otherwise Specified (NOTE 2) TEST LEVEL A A A A A A A A A A A A A A A C A B B B A B B C TEMP (oC) Full Full Full Full Full Full Full Full Full Full Full Full Full 25 25 25 25 25 25 25 Full 25 25 25 MIN 2.0 -0.2 -200 -150 -300 0 0 0 -20 0 -20 0.8 1.85 10 TYP 80 0.8 -65 -30 -95 50 80 15 1 110 0.1 1.1 2.1 410 0.5 400 1.5 2 2.0 800 1.6 MAX 112 1.5 VCC 0.8 0 0 0 200 300 150 20 300 20 2.2 2.0 2.15 UNITS mA mA V V A A A A A A A A A V V mA ns s s V V/oC mV/V k
High Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 2.4V High Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pins 16 and 21 with VIN = 0.8V High Level Input Current at 5.5V VCC for pin 17, with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 17, with VIN = 4.0V Low Level Input Current at 5.5V VCC for pin 17, with VIN = 0.8V High Level Input Current at 5.5V VCC for pin 43 with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 43 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pin 43 with VIN = 0.8V VAGC Input for Max Gain (Note 5) VAGC Input for Min Gain (Note 5) VAGC Control Input Impedance (Per Stage) (Note 3) VAGC Control Input Current (Per Stage) at Max Control Voltage Full Range AGC Switching Large Signal Recovery (Note 4) Full Range AGC Switching 1dB Settling Time (Note 4) Power Down/Up Switching Speed (Note 4) Reference Voltage Reference Voltage Variation Over Temperature Reference Voltage Variation Over Supply Voltage Reference Voltage Minimum Load Resistance NOTES: 2. A = Production Tested, B = Based on Characterization, C = By Design. 3. 1.2V reference source in series with 410. 4. Determined by external components. 5. Measured at probe.
7
HFA3766
Cascaded AC Electrical Specifications, Demodulator Chain Performance
IF = 280 MHz, Unless Otherwise Specified PARAMETER CASCADED CHARACTERISTICS Cascaded Power Gain Cascaded OIP3 Cascaded Noise Figure Cascaded Output 1dB Compression TBD TBD IF Demodulator I and Q Outputs Voltage Swing (IF input Range of -70dBm to -30dBm) IF Demodulator I and Q Channels Output Drive Capability (ZOUT = 50) CMAX = 10pF, VOUT = 500mVP-P IF Demodulator I/Q Amplitude Balance, IFin = -50dBm at 50 IF Demodulator I/Q Phase Balance, IFin = -50dBm at 50 IF Demodulator Output, P1dB NOTES: 6. A = Production Tested, B = Based on Characterization, C = By Design. 7. Determined by external components. A C A A TBD TBD TBD TBD TBD TBD TBD TBD Full 25 Full Full TBD TBD TBD TBD TBD TBD 1.2 -1.0 -4.0 TBD TBD TBD TBD TBD TBD 250 2 0 0 TBD TBD TBD TBD TBD TBD +1.0 +4.0 TBD TBD TBD TBD TBD TBD mVP-P k dB Degrees mV (NOTE 6) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS VCC = 3.0V, LO = 560 MHz, and
AC Electrical Specifications, Modulator Performance
PARAMETER IF Modulator I/Q Amplitude Balance (Note 9) IF Modulator I/Q Phase Balance (Note 9) IF Modulator SSB Output Power (Note 10) IF Modulator Side Band Suppression (Note 10) IF Mod Carrier Suppression (LO Buffer Enabled) (Note 10) IF Mod Carrier Suppression (LO Buffer Disabled) (Note 10) IF Modulator Output Noise Floor (Out of Band) IF Modulator I/Q 3dB Cutoff SEL0/1 = 2.2MHz (Note 11) IF Modulator I/Q 3dB Cutoff SEL0/1 = 4.4MHz (Note 11) IF Modulator I/Q 3dB Cutoff SEL0/1 = 8.8MHz (Note 11) IF Modulator I/Q 3dB Cutoff SEL0/1 = 17.6MHz (Note 11) IF Modulator Spread Spectrum Output Power (Note 12) IF Modulator Side Lobe to Main Lobe Ratio, LPF = 8.8MHz (Note 12) NOTES:
VCC = 3.0V, Unless Otherwise Specified (NOTE 8) TEST LEVEL B B A A A B B A A A A B A TEMP (oC) 25 25 Full Full Full 25 25 Full Full Full Full 25 Full MIN -1.0 -4.0 -12 26 28 28 1.8 3.6 7.3 14.6 -12 32 TYP 0 0 -7 33 30 36 -132 2.2 4.4 8.8 17.6 -7 35 MAX +1.0 +4.0 -4 2.5 5.0 9.8 19.6 -4 UNITS dB Degrees dBm dBc dBc dBc dBm/Hz MHz MHz MHz MHz dBm dB
SYMBOL Mabal Mphbal Mssbpw Mssbss Mssbcs Mssbcs1 Moutn0 Msel1f Msel2f Msel3f Msel4f Mdsspw Mdsssl
8. A = Production Tested, B = Based on Characterization, C = By Design. 9. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB characteristics. 10. Power at the fundamental SSB frequency of two 6MHz, 90 degrees apart square waves applied at TXI and TXQ inputs. VIH = 3.0V, VIL = 0.5V. LPF selected to 8.8MHz cutoff. 11. Cutoff frequencies are specified for both modulator and demodulator as the filter bank is shared and multiplexed for Transmit and Receive. Data is characterized by observing the attenuation of the fundamental of a square wave digital input swept at each channel separately. The IF output is down converted by an external wideband mixer with a coherent LO input for each of quadrature signals separately. 12. Typical ratio characterization with RTUNE set to 7.7MHz, LPF selected for 8.8MHz. TXI and TXQ Digital Inputs at two independent and aligned 11M chip/s, 223-1 sequence code signals.
8
HFA3766
AC Electrical Specifications, Cascaded AGC Stages Performance
PARAMETER Frequency Range (Note 14) Voltage Gain at Max Gain (Note 15) (VAGC = 0.8V, RS = 50, RL = 500) Voltage Gain at Min Gain (VAGC = 2.1V, RS = 50, RL = 500) Noise Figure at Max Gain, RS = 50 Output P 1dB at Min Gain, RS = 50, dBm into RL = 500 Input P 1dB at Min Gain, RS = 50 Output IP3 at Min Gain, dBm into RL = 500 Input IP3 at Min Gain, RS = 50 Group Delay, 20MHz Bandwidth Single Ended Input Impedance, AGC_SEL = floating Differential Input Impedance, AGC_SEL = ground Differential Output Impedance NOTES: 13. A = Production Tested, B = Based on Characterization, C = By Design. 14. Determined by external components. 15. Measured at probe. (NOTE 13) TEST LEVEL B B B B B B B B B B B B VCC = 3.0V MIN 10 78 -16 -13 -5 -2 TYP 82 7 10 -13 -10 -2 1 2.0 50 100 80 MAX 400 11 UNITS MHz dB dB dB dBm dBm dBm dBm nsP-P
TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 25 25
AC Electrical Specifications, I/Q Down Converter Individual Performance
PARAMETER Quadrature Demodulator Input Frequency Range Demodulator Baseband I/Q Frequency Range Demodulator Voltage Gain at Frequency Range Demodulator Differential Input Resistance Demodulator Differential Input Capacitance Demodulator Differential Output Level at 4K Load, (Output Controlled By AGC Action) Demodulator Amplitude Balance Demodulator Phase Balance at 286MHz Demodulator Phase Balance at 400MHz Demodulator Output 1dB Compression Voltage at 4K Load NOTE: 16. A = Production Tested, B = Based on Characterization, C = By Design. (NOTE 16) TEST LEVEL B C B C C B B B B B TEMP. (oC) 25 25 25 25 25 25 25 25 25 25
VCC = 3.0V MIN 10 6 400 -1.0 -4 -4 TYP 8 1 0.5 500 1.25 MAX 400 30 9 560 1.0 4 4 UNITS MHz MHz dB k pF mVP-P dB Degrees Degrees VP-P
AC Electrical Specifications, LO Individual Performance
PARAMETER 2XLO Input Frequency Range (2 X Input Range) 2XLO Input Current Range 2XLO Input Impedance Buffered LO Output Voltage, Single Ended
VCC = 3.0V TEMP. (oC) 25 25 25 25 MIN 20 50 50 TYP 200 130 100 MAX 800 300 UNITS MHz ARMS mVP-P
(NOTE 17) TEST LEVEL B C C C
9
HFA3766
AC Electrical Specifications, LO Individual Performance
PARAMETER Buffered LO Output Impedance Quadrature IF Modulator Output Frequency Range IF Modulator I/Q Input Frequency Range IF Modulator Differential I/Q Max Input Voltage IF Modulator Differential I/Q Input Impedance IF Modulator Differential Input Capacitance IF Modulator I/Q Amplitude Balance IF Modulator I/Q Phase Balance at 200MHz IF Modulator I/Q Phase Balance at 400MHz IF Modulator Output at SSB Into 50, I and Q, 500mVP-P IF Modulator Carrier Suppression (LO Buffer Enabled) IF Modulator Carrier Suppression (LO Buffer Disabled) IF Modulator SSB Sideband Suppression at 200MHz IF Modulator SSB Sideband Suppression at 400MHz IF Output Level Compression Point IF Modulator Intermodulation Suppression NOTE: 17. A = Production Tested, B = Based on Characterization, C = By Design. VCC = 3.0V (Continued) TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 MIN 10 -0.5 -2 -4 -22 28 28 28 26 26 TYP 50 2.25 4 0.5 30 36 1.0 MAX 400 30 0.5 2 4 -10.0 UNITS MHz MHz VP-P k pF dB Degrees Degrees dBm dBc dBc dBc dBc VP-P dBc
(NOTE 17) TEST LEVEL C B C C C C A A B A A A A B C B
AC Electrical Specifications, RX 5TH Order LPF Cascaded Performance
PARAMETER RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 RX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 RX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 RX LPF Sel0, Sel1 Tuning Speed RX LPF 3dB Bandwidth Tuning LPF Tune Nominal Resistance RX LPF Voltage Gain RX LPF DC Output Voltage TX/RX Offset Voltage RX LPF Single Ended Output Voltage Swing at 2k Load (Controlled By AGC Action) RX LPF Differential Input Impedance RX I/Q Channel Amplitude Match RX I/Q Channel Phase Match RX LPF Total Harmonic Distortion LPF Output Impedance, Single-Ended NOTE: (NOTE 18) TEST LEVEL D D D D B D B D A A B C C C A C
VCC = 3.0V MIN 1.8 3.6 7.4 14.8 -20 -1.0 TBD 4 -1 -4 TYP 2.20 4.40 8.80 17.60 787 0 1.3 0 5 3 50 MAX 2.4 4.8 9.6 19.2 1 +20 1.0 TBD 550 1 4 6 UNITS MHz MHz MHz MHz s % dB V V mVP-P k dB Degrees %
TEMP. (oC) 25 25 25 25 25 25 25 25 25 25 25 25 Full Full 25 25
18. A = Production Tested, B = Based on Characterization, C = By Design D = Measured at Probe.
10
HFA3766
TABLE 1. LOW PASS FILTER PROGRAMING AND TUNING INFORMATION MODE BW0 BW1 BW2 BW3 LPF SEL1 0 0 1 1 LPF SEL0 0 1 0 1 f3dB (NOMINAL RTUNE) 2.2MHz 4.4MHz 8.8MHz 17.6MHz
f 3dBNOMINAL 787 f TUNED 3dB = ---------------------------------------------------------R TUNE
PERCENT OF NOMINAL FREQUENCY
+20%
-20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 +20 +25 +30
[(787 - RTUNE)/RTUNE] * 100%
FREQUENCY 20% Low Nominal 20% High
RTUNE 984 787 656
FIGURE 1. TYPICAL f 3dB vs RTUNE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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